Mastering High-Density Interconnect Routing: From Microvia Planning to Reliable HDI Fanouts

Routing a high-density interconnect circuit board is a fundamentally different exercise from routing a conventional multilayer PCB. The reduced pad pitch, fine-pitch BGAs, and increased pin counts demand a routing strategy that starts long before the first trace is drawn. A successful HDI layout depends on selecting the right via architecture, planning escape routing around tight component placements, and validating the design against both signal integrity and manufacturing constraints. When designers approach HDI routing as an integrated process rather than a series of isolated fixes, they can lower layer count, improve yield, and achieve cleaner power distribution.

What Makes HDI PCB Routing Different from Conventional PCB Design

Conventional PCB routing relies primarily on mechanically drilled through-hole vias that span the entire board. HDI routing, by contrast, uses laser-drilled microvias, blind vias, buried vias, and often via-in-pad structures to create shorter, more direct interconnections. These features allow signals to move between adjacent layers without consuming routing space on every layer. Because microvias are formed with laser ablation rather than mechanical drilling, they have a much smaller capture pad and hole diameter. This enables escape routing from components with 0.4 mm pitch or finer, which would be nearly impossible with traditional through-hole vias.

However, the physical and manufacturing rules are also different. A laser microvia typically spans only one or two dielectric layers, so the designer must think in terms of layer pairs and sequential lamination. The aspect ratio of a microvia—the relationship between hole depth and diameter—is much lower than that of a mechanically drilled via, but it still has a direct impact on plating reliability and signal performance. If a designer places microvias without considering the subsequent lamination cycle, the board may require extra layers, suffer from resin voiding, or create stress points that reduce long-term reliability. This is why HDI routing starts with a clear via map before any dense area fanout is attempted.

Designers should also recognize that HDI routing changes the value of every square millimeter. In a conventional board, a crowded escape route can often be solved by adding a layer. In HDI, adding layers is expensive and can change the entire via architecture. A better approach is to optimize the existing layer pairs, use finer trace widths where impedance allows, and reserve microvia transitions for the shortest possible connections. Engineers who are new to this flow can reduce missteps by reviewing a structured sequence in How To Route HDI PCB before finalizing the stackup. That structured view helps align via selection, pad geometry, and fanout strategy with actual fabrication capabilities.

HDI Stackup Planning, Via Architecture, and Fanout Strategies

The foundation of any HDI routing effort is the stackup. Common HDI builds include 1+N+1, 2+N+2, and any-layer or every-layer interconnect structures. A 1+N+1 stackup uses one microvia layer on each side of a conventional core, while a 2+N+2 build adds a second microvia layer for greater routing freedom. Any-layer HDI, often used in smartphones and advanced automotive modules, allows microvias to connect between any adjacent layers, producing the highest routing density but also requiring more sequential lamination steps and tighter registration control.

Selecting the right architecture should begin with the component pitch and the number of I/Os requiring escape. For a 0.5 mm pitch BGA, a 1+N+1 stackup may be sufficient if the inner layers are used efficiently. For a 0.35 mm pitch package or a high-pin-count processor, a 2+N+2 or any-layer structure may be necessary. Once the architecture is chosen, the designer should define the via pad stack for each layer pair. Microvia capture pads must be large enough for laser alignment and plating but small enough to fit between adjacent BGA balls. This balance directly affects yield and the ability to use via-in-pad.

Fanout strategy is where good HDI routing becomes visible. The most common approaches include dog-bone fanout, where a short trace connects a BGA pad to a nearby via, and via-in-pad, where the microvia sits directly under the component pad. Dog-bone fanout is simpler and lower cost, but it consumes more space. Via-in-pad is preferred for fine-pitch components because it minimizes the escape area and improves signal integrity by reducing stub length and via inductance. When via-in-pad is used, the fabricator must fill the via with conductive or non-conductive epoxy, plate it over, and planarize the surface to support component soldering. This is an important DFM consideration that should be locked early in the routing cycle.

Another powerful technique is the use of skip vias or stacked microvias to move signals from an outer layer to a deeper layer without passing through every intermediate layer. These structures shorten return paths and free up routing channels, but they also require precise layer registration and additional drilling or plating passes. In dense HDI designs, combining stacked microvias on critical signals with staggered microvias elsewhere can help control cost while still meeting performance targets. The key is not to apply every via type uniformly, but to assign high-performance via structures only where they produce measurable benefits.

Signal Integrity, DFM, and Verification for Reliable HDI Routing

HDI routing is not just about making connections; it is about making connections that preserve signal quality. The same density that enables compact designs also increases crosstalk, impedance discontinuities, and return path disruption. Microvias have lower parasitic inductance than through-hole vias, which is an advantage for high-speed signals, but only if the reference plane is continuous and the via transition is short. When routing differential pairs through an HDI stackup, the designer should keep the pair on the same layer pair, match the length, and avoid splitting the pair across different via structures unless absolutely necessary. A ground reference via near every signal layer transition helps maintain a controlled impedance path and reduces common-mode noise.

Power distribution also requires attention. In dense HDI boards, large power planes may become heavily perforated by microvias and clearance holes, which can create high-resistance paths and worsen voltage drop. Designers should use multiple power vias for high-current devices, maintain adequate copper web between anti-pads, and simulate the power delivery network where possible. For high-frequency or RF sections, placing microvias closer to the component pad and minimizing pad size can reduce parasitic capacitance and improve return loss. These practices are especially relevant in compact medical devices, automotive radar modules, and high-speed telecom equipment where reliability margins are narrow.

DFM verification should run in parallel with routing, not as an afterthought. A useful practice is to create separate design rule classes for microvias, buried vias, and through-hole vias. This allows the designer to check minimum annular ring, hole-to-copper spacing, and layer-specific via spans independently. Many HDI failures occur not because a trace cannot be routed, but because the final geometry violates the fabricator’s laser drill registration tolerance or plating capability. The designer should verify that stacked microvias are aligned, that blind vias do not create unintended drill depth violations, and that via-in-pad structures meet fill and cap requirements. Working with a fabricator that understands sequential lamination and laser drilling early in the design phase prevents costly re-spins and ensures the routed HDI board can be manufactured in volume.

Consider an automotive ADAS processing board with a 0.4 mm pitch BGA, multiple high-speed differential pairs, and strict thermal reliability requirements. If the layout team starts by routing the BGA escape with conventional through-holes, the fanout becomes unmanageable and the ground return paths degrade. Instead, the team uses a 2+N+2 stackup with via-in-pad on the outer rows, stacked microvias for critical differential signals, and dog-bone fanout on less dense areas. Signal integrity simulation validates the return path, and DFM checks confirm that laser-drilled microvia capture pads remain within tolerance. The result is a routable board that meets both electrical and manufacturing requirements without adding unnecessary layers.

Théo Legrand

Marseille street-photographer turned Montréal tech columnist. Théo deciphers AI ethics one day and reviews artisan cheese the next. He fences épée for adrenaline, collects transit maps, and claims every good headline needs a soundtrack.